这张图片是mealy型状态机的结构，Moore型类似，输出与输入无关。

一段式

module moduleName (input clk,input rst_n,input in,output reg [3:0]	out
);localparam s1=4'd0, s2=4'd1, s3=4'd2, s4=4'd3, s5=4'd4;
reg [3:0] cur_state;
reg [3:0] next_state;always @(posedge clk) beginif(!rst_n) begincur_state <= s1;endelse	begincase (cur_state)s1:beginif(in)cur_state <= s2;out <= cur_state;ends2:beginif(~in)cur_state <= s3;out <= cur_state;ends3:beginif(in)cur_state <= s4;out <= cur_state;ends4:beginif(~in)cur_state <= s5;out <= cur_state;ends5:beginif(in)cur_state <= s1;out <= cur_state;enddefault: begincur_state <= s1;out <= cur_state;endendcaseend
endendmodule

如果将输出单独用组合逻辑表示，本质上也是一段式状态机

缺点是，输出比状态晚一个时钟

两段式

module moduleName (input clk,input rst_n,input in,output reg [3:0]	out
);localparam s1=4'd0, s2=4'd1, s3=4'd2, s4=4'd3, s5=4'd4;
reg [3:0] cur_state;
reg [3:0] next_state;// ========================================
// 二段式
// ========================================
always @(posedge clk) beginif(!rst_n)	begincur_state <= s1;endelse	begincur_state <= next_state;end
endalways @(*) begincase (cur_state)s1:beginif(in)cur_state = s2;out = cur_state;ends2:beginif(~in)cur_state = s3;out = cur_state;ends3:beginif(in)cur_state = s4;out = cur_state;ends4:beginif(~in)cur_state = s5;out = cur_state;ends5:beginif(in)cur_state = s1;out = cur_state;enddefault: begincur_state = s1;out = cur_state;endendcase
end

如果将输出单独用组合逻辑表示，本质上也是二段式状态机

输出和状态的时序是一致的

三段式

module moduleName (input clk,input rst_n,input in,output reg [3:0]	out
);localparam s1=4'd0, s2=4'd1, s3=4'd2, s4=4'd3, s5=4'd4;
reg [3:0] cur_state;
reg [3:0] next_state;// ========================================
// 三段式
// ========================================always @(posedge clk) beginif(!rst_n)	begincur_state <= s1;endelse	begincur_state <= next_state;end
endalways @(*) begincase (cur_state)s1:beginif(in)next_state = s2;ends2:beginif(~in)next_state = s3;ends3:beginif(in)next_state = s4;ends4:beginif(~in)next_state = s5;ends5:beginif(in)next_state = s1;enddefault: beginnext_state = s1;endendcase
end`ifdef SEQUENTIAL_LOGICalways @(posedge clk) beginif(!rst_n)	beginout <= 4'd0;endelse	begincase (next_state)s1:beginout <= s1;ends2:beginout <= s2;ends3:beginout <= s3;ends4:beginout <= s4;ends5:beginout <= s5;enddefault: beginout <= s1;endendcaseendend
`elsealways @(*) beginif(!rst_n)	beginout <= 4'd0;endelse	begincase (cur_state)s1:beginout <= s1;ends2:beginout <= s2;ends3:beginout <= s3;ends4:beginout <= s4;ends5:beginout <= s5;enddefault: beginout <= s1;endendcaseend
end`endif

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